Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a nonvolatile memory device using in-situ photoresist slimming.
To increase the device density when a design rule decreases, a flash memory device employs a method of using a three-dimensional (3D) structure instead of an existing floating gate.
Meanwhile, a photolithography process used to fabricate a semiconductor device, such as a flash memory device, necessarily requires a photo-mask to form a pattern. This photo-mask is formed to selectively allow light to pass according to patterns of various shapes using a light blocking material on the surface of a light-transmitting substrate, wherein the patterns correspond to integrated circuits to be formed.
Thus, desired patterns are exactly transcribed on the photoresist when performing the alignment exposure in the photolithography process. However, this method for forming the mask has a disadvantage in that a desired line width is not sufficiently obtained because of the interference between patterns formed on the photo-mask. As a line width of a circuit of the semiconductor device becomes narrower, and thus, as a wavelength of a light source for the exposure is shortened, it becomes more difficult to obtain a desired line width of the photo-mask.
That is, a pattern in a line shape whose line width is relatively fine is affected by the density of patterns around it. Therefore, although a pattern is formed on the mask to have a normal line width, the size of the pattern is changed by the diffraction of light when forming the pattern on the photoresist through the exposure step in a photolithography process. Especially, in the case that a light proximity effect of a mask pattern is not considered properly, the line width of the pattern is distorted contrary to the original intent of the exposure in the lithography process. Thus the linearity of the line width is distorted, resulting in a negative influence on properties of the semiconductor device.
As illustrated in FIG. 1, in the prior art, the slimming of the photoresist was not properly achieved when performing a slimming etching process after a mask process. As a result, it was difficult to form a pattern in a step shape, and the line edge roughness (LER) was generated.
Namely, in case a pattern is formed by a method for forming a fine pattern using an existing lithography process, the LER A illustrated in FIG. 1 is formed by a mask error occurring in the mask drawing and a structure of the resist.
The generation of the LER A affects subsequent processes, such as an etching process, and, negatively influences electrical properties, especially a threshold voltage, of the semiconductor device, as shown in FIG. 2. Therefore, lots of research and development of processes are in progress to minimize the generation of the LER when forming a pattern.
The typical LER is usually generated in the resist of a chemical amplifying type applied to KrF, ArF, 157 nm, EUV, or E-beam. That is, the LER is mainly generated by a chemical reaction between matrix resin and the resist, and the non-uniform diffusion of the acid generated in the exposure, and also caused by a non-uniform developing mechanism with a developer that is used.
Furthermore, the LER may be generated by performing a patterning process using a mask. Because the selection of a mask material and a light source on a mask fabricated to form a pattern whose size is getting smaller, the LER may be transcribed on a pattern when performing a patterning process using the mask. Therefore, the selection of a photoacid generator applied to induce the uniform diffusion of the acid is important when using the chemical amplifying type resist. Also, it may be required to process and apply an acid capable of controlling the influence for the exposure and the post exposure baking.
However, the LER is inevitably generated in a process of applying the chemical amplifying type resist in spite of lots of research and improvement of the processing requirement. Therefore, a current concern is how much the LER can be minimized using a subsequent process. The generation of the LER when forming the fine pattern causes a big concern to the properties of the semiconductor device, and thus, it is difficult to expect the stabilization of the process.